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are trademarks of their respective owners.

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KEY FEATURES

○

Master and Multi-master operations

○

Two modes of operation: SPI mode and

FIFO mode

○

8 SPI slave select lines

○

System error detection

○

Interrupt generation

○

Supports speeds up 1/8 of system clock

○

Bit rates generated 1/8 - 1/1024 of system

clock.

○

Four transfer formats supported

○

Simple interface allows easy connection to

microcontrollers

○

Slave operation

○

Two modes of operation: SPI mode and

FIFO mode

○

System error detection

○

Interrupt generation

○

Supports speeds up ¼ of system clock

○

Simple interface allows easy connection to

microcontrollers

○

Four transfer formats supported

transfer

are each buffered with 16/64 byte FIFO's

to reduce the number of interrupts pre-

sented to the CPU

or 512 Bytes

design with no internal tri-states

CONFIGURATI O N

The following parameters of the DSPI_FIFO

core can be easy adjusted to requirements of

dedicated application and technology. Con-

figuration of the core can be prepared by ef-

fortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- enable

- disable

- standard 16/64

- large up to 512

•

SLAVE SELECT

SETUP TIME

-

Number of CLK periods

of SSO low before SPI

starts transmission

•

SLAVE SELECT

HIGH TIME

-

Number of CLK periods

of SSO High between two

consecutive master

transmissions.

•

SLAVE SELECT

HOLD TIME

-

Number of CLK periods

of SSO low after end of

SPI master transmission

DELIVERABLES

♦

Source code:

◊

VHDL Source Code or/and

◊

VERILOG Source Code or/and

◊

Encrypted, or plain text EDIF netlist

♦

VHDL & VERILOG test bench environ-

ment

◊

Active-HDL automatic simulation macros

◊

ModelSim automatic simulation macros

◊

Tests with reference responses

♦

Technical documentation

◊

Installation notes

◊

HDL core specification

◊

Datasheet

♦

Synthesis scripts

♦

Example application

♦

Technical support

◊

IP Core implementation support

◊

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

●

Phone & email support