All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

D

1

●

●

●

●

●

●

●

●

●

●

●

●

Pipelined High Performance

8-bit Microcontroller

ver 4.03

OVERVIEW

DP8051 is an ultra high performance,

speed optimized

soft core of a single-chip 8-

bit embedded controller dedicated for opera-

tion with fast (typically on-chip) and slow (off-

chip) memories. The core has been designed

with a special concern about performance to

power consumption

ratio. This ratio is ex-

tended by an advanced power management

unit PMU.

DP8051 soft core is 100% binary-

compatible with the industry standard 8051 8-

bit microcontroller. There are two configura-

tions of DP8051: Harward where internal data

and program buses are separated, and von

Neumann

with common program and external

data bus. DP8051 has Pipelined RISC archi-

tecture 10 times faster compared to standard

architecture and executes 85-200 million in-

structions

per second. This performance can

also be exploited to great advantage in low

power

applications where the core can be

clocked over ten times more slowly than the

original implementation for no performance

penalty.

DP8051 is delivered with fully automated

testbench

and complete set of tests allowing

easy package validation at each stage of SoC

design flow.

CPU FEATURES

100% software compatible with industry

standard 8051

Pipelined RISC architecture enables to

execute instructions 10 times faster com-

pared to standard 8051

24 times faster multiplication

12 times faster addition

Up to 256 bytes of internal (on-chip) Data

Memory

Up to 64K bytes of internal (on-chip) or

external (off-chip) Program Memory

Up to 16M bytes of external (off-chip) Data

Memory

User programmable Program Memory Wait

States solution for wide range of memories

speed

User programmable External Data Memory

Wait States solution for wide range of

memories speed

De-multiplexed Address/Data bus to allow

easy connection to memory

Dedicated signal for Program Memory

writes.

Interface for additional Special Function

Registers