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depends on memory access time and DP8051

clock frequency.

0x0400

0xF000

On-chip Memory

(implemented as ROM)

On chip Memory

(implemented as RAM)

Off chip Memory

(implemented as ROM,

SRAM or FLASH)

0x0000

0xFFFF

In most cases the proper number of Wait-

States cycles is between 2-5. The READY pin

can be also dynamically modulated e.g. by

SDRAM controller.

The figure below shows a typical Program

Memories connections in system with DP8051

Microcontroller core.

10

12

8

prgaddr

On-chip Memory

(implemented as ROM)

0 Wait-State access

On-

chip Memory

(implemented as RAM)

0 Wait-State access

prgromdata

i

prgramdatai

prgdatao

prgramwr

8

xdatai

8

8

xdatao

xaddr

16

xprgrd

xprgwr

Off-chip Memory

(implemented as

FLASH, or SRAM)

eg. 2-5 Wait-State

access

ASIC or FPGA

chip

ready

Wait-States

manager

DP8051

rsto

The described above implementation should be

treated as an example. All Program Memory

spaces are fully configurable. For timing-critical

applications whole program code can be imple-

mented as on-chip ROM and (or) RAM and

executed without Wait-States, but for some

other applications whole program code can be

implemented as off-chip ROM or FLASH and

executed with required number Wait-State cy-

cles.

PERFORMANCE

The following tables give a survey about the

Core area and performance in Programmable

Logic Devices after Place & Route (CPU fea-

tures and peripherals have been included):

Device

Speed grade

FLEX10KE

-1

57 MHz

ACEX1K

-1

57 MHz

APEX20K

-1

50 MHz

APEX20KE

-1

66 MHz

APEX20KC

-7

78 MHz

APEX-II

-7

76 MHz

MERCURY

-5

100 MHz

CYCLONE

-6

91 MHz

CYCLONE-II

-6

93 MHz

STRATIX

-5

90 MHz

STRATIX-II

-3

160 MHz

Core performance in ALTERA® devices

For a user the most important is application

speed improvement. The most commonly used

arithmetic functions and theirs improvement

are shown in table below. Improvement was

computed as {80C51 clock periods} divided by

{DP8051 clock periods} required to execute an

identical function. More details are available in

core documentation.

Function

Improvement

8-bit addition (immediate data)

9,00

8-bit addition (direct addressing)

9,00

8-bit addition (indirect addressing)

9,00

8-bit addition (register addressing)

12,00

8-bit subtraction (immediate data)

9,00

8-bit subtraction (direct addressing)

9,00

8-bit subtraction (indirect addressing)

9,00

8-bit subtraction (register addressing)

12,00

8-bit multiplication

16,00

8-bit division

9,60

16-bit addition

12,00

16-bit subtraction

12,00

16-bit multiplication

13,60

32-bit addition

12,00

32-bit subtraction

12,00

32-bit multiplication

12,60

Average speed improvement:

11,12

Dhrystone Benchmark Version 2.1 was used to

measure Core performance. The following ta-

ble gives a survey about the DP8051 perform-

ance in terms of Dhrystone/sec and VAX MIPS

rating.

Device

Target

Clock

fre-

quency

Dhry/sec

(VAX MIPS)

80C51

-

12 MHz

268 (0.153)

80C310

-

33 MHz

1550 (0.882)