TMPR3911 datasheet(7/462 Pages) TOSHIBA

7 / 462 page

Table of Contents

iii

6.2.2

Clock Module Description ......................................................................................................................6-5

6.3

Clock Registers...............................................................................................................................................6-6

6.3.1

Clock Control Register............................................................................................................................6-6

7. CHI Module.............................................................................................................................................................7-1

7.1

Overview ........................................................................................................................................................7-1

7.1.1

Related Pins.............................................................................................................................................7-1

7.2

Interface Requirements...................................................................................................................................7-2

7.2.1

Frame Structure and Serial Timing .........................................................................................................7-2

7.2.2

Configurations.........................................................................................................................................7-7

7.3

Implementation...............................................................................................................................................7-8

7.3.1

Block Diagram ........................................................................................................................................7-8

7.3.2

Transmitter ..............................................................................................................................................7-9

7.3.3

Receiver...................................................................................................................................................7-9

7.3.4

Clock and Control Generation...............................................................................................................7-10

7.3.5

DMA Address Generation.....................................................................................................................7-12

7.3.6

Related Interrupts ..................................................................................................................................7-14

7.4

CHI Registers ...............................................................................................................................................7-15

7.4.1

CHI Control Register ............................................................................................................................7-15

7.4.2

CHI Pointer Enable Register .................................................................................................................7-18

7.4.3

CHI Receive Pointer A Register ...........................................................................................................7-20

7.4.4

CHI Receive Pointer B Register............................................................................................................7-21

7.4.5

CHI Transmit Pointer A Register ..........................................................................................................7-22

7.4.6

CHI Transmit Pointer B Register ..........................................................................................................7-23

7.4.7

CHI Size Register..................................................................................................................................7-24

7.4.8

CHI RX Start Register...........................................................................................................................7-25

7.4.9

CHI TX Start Register...........................................................................................................................7-25

7.4.10

CHI TX Holding Register .....................................................................................................................7-26

7.4.11

CHI RX Holding Register .....................................................................................................................7-26

8. Interrupt Module......................................................................................................................................................8-1

8.1

Overview ........................................................................................................................................................8-1

8.2

Implementation...............................................................................................................................................8-2

8.2.1

Block Diagram ........................................................................................................................................8-2

8.2.2

Interrupt Logic Description .....................................................................................................................8-3

8.3

Interrupt Registers ..........................................................................................................................................8-5

8.3.1

Interrupt Status 1 Register.......................................................................................................................8-5

8.3.2

Interrupt Status 2 Register.......................................................................................................................8-8

8.3.3

Interrupt Status 3 Register.....................................................................................................................8-11

8.3.4

Interrupt Status 4 Register.....................................................................................................................8-11

8.3.5

Interrupt Status 5 Register.....................................................................................................................8-12

8.3.6

Interrupt Status 6 Register.....................................................................................................................8-15

8.3.7

Clear Interrupt 1 Register ......................................................................................................................8-16

8.3.8

Clear Interrupt 2 Register ......................................................................................................................8-16

8.3.9

Clear Interrupt 3 Register ......................................................................................................................8-16

8.3.10

Clear Interrupt 4 Register ......................................................................................................................8-16

8.3.11

Clear Interrupt 5 Register ......................................................................................................................8-16

8.3.12

Enable Interrupt 1 Register....................................................................................................................8-16

8.3.13

Enable Interrupt 2 Register....................................................................................................................8-17

8.3.14

Enable Interrupt 3 Register....................................................................................................................8-17

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