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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR3911 датащи(PDF) 67 Page - Toshiba Semiconductor |
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TMPR3911 датащи(HTML) 67 Page - Toshiba Semiconductor |
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67 / 462 page  Chapter 2 Pin Descriptions 2-13 2.2.13 Endian Pin ENDIAN: INPUT This pin is used to select the endianness. The high level input sets the endianness to the big endian. The low level input sets the endianness to the little endian. 2.2.14 Test Pins TESTAIU: INPUT If this pin is set to low during reset, ROM data bus width will be 16 bits wide. If this pin is set to high during reset, ROM data bus width will be 32 bits wide. When the DREQ* signal is asserted to request external arbitration, this pin must be set to low. TESTCPU: INPUT Connect to GND. TESTIN: INPUT Connect to GND. 2.2.15 Spare Pins NC3-1: NO CONNECT These pins are reserved for future use and should be left unconnected. 2.2.16 Power Supply Pins VDD: +3.3 V These pins are the power pins. (In case of TMRP3912AU-92 and TMRP3912XB-92) VSS: GND These pins are the ground pins for the TMPR3911/12. VDDH: +3.3 V These pins are the power pins for I/O. (In case of TMPR3911BU and TMPR3911BXB) VDDL: +2.6 V These pins are the power pins for internal logic. (In case of TMPR3911BU and TMPR3911BXB) VDD (PLL): +2.6 V These pins are the power pins for PLL. (In case of TMPR3911BU and TMPR3911BXB) VSS (PLL): GND These pins are the ground pins for PLL. (In case of TMPR3911BU and TMPR3911BXB) |
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