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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR3911 датащи(PDF) 45 Page - Toshiba Semiconductor |
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TMPR3911 датащи(HTML) 45 Page - Toshiba Semiconductor |
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45 / 462 page  Chapter 1 TMPR3911/12 Overview 1-3 Figure 1.1.2 shows a block diagram of the TMPR3911/12. The key functions and features for each TMPR3911/12 module are itemized below. Processor core Module • TX39/H Processor core • full 32-bit operation (registers, instructions, addresses, etc.) • 32 general purpose 32-bit registers; 32-bit program counter • MIPS RISC Instruction Set Architecture (ISA) supported • Translation Look-aside Buffer (TLB) (4K Page size, 32 entries) • on-chip cache • 4 Kbyte instruction cache (I-cache) • physical address tag and valid bit per cache line • programmable burst size • instruction streaming mode supported • direct-mapped • 1 Kbyte data cache (D-cache) • physical address tag and valid bit per cache line • programmable burst size • write-through • two-way set associative • cache address snoop mode supported for DMA • 4-level deep write buffer • high-speed multiplier/accumulator • on-chip hardware multiplier • supports 32 × 32 multiplier operations, with 64-bit accumulator • existing multiply instructions are enhanced and new multiply and add instructions are added to the R3000A instruction set to improve the performance of DSP applications • Processor core interface • handles data bus, address bus, and control interface between Processor core and rest of the TMPR3911/12 logic |
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