TMS320DM6435 datasheet(87/252 Pages) TI

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TMS320DM6435

Digital Media Processor

SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007

Table 3-17. TIMERCTL Register Description (continued)

Bit

Field Name

Description

WatchDog Reset Enable

WDRST

0 = WatchDog Timer Event (WDINT from Timer2) does not cause device reset.

1 = WatchDog Timer Event (WDINT from Timer2) causes a device max reset (default).

3.6.2.3 EDMA TC Configuration Register (EDMATCCFG)

The EDMA Transfer Controller Configuration (EDMATCCFG) register configures the default burst size

(DBS) for EDMA TC0, EDMA TC1, and EDMA TC2. For more information on the correct usage of DBS,

see the TMS320DM643x DMP Enhanced Direct Memory Access (EDMA) Controller User's Guide

(literature number SPRU987). The user should only modify this register once during device

initialization and when the corresponding EDMA TC is not in use.

RESERVED

R-0000 0000 0000 0000

RESERVED

TC2DBS

TC1DBS

TC0DBS

R-0000 0000 00

R/W-10

R/W-01

R/W-00

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-10. EDMATCCFG Register— 0x01C4 0088

Table 3-18. EDMATCCFG Register Description

Bit

Field

Description

31:6

RESERVED Reserved. Read-Only, writes have no effect.

EDMA TC2 Default Burst Size

00 = 16 byte

01 = 32 byte

10 = 64 byte (default)

5:4

TC2DBS

11= reserved

EDMA TC2 is intended for miscellaneous transfers.

TC2 FIFO size is 128 bytes, regardless of Default Burst Size setting.

EDMA TC1 Default Burst Size

00 = 16 byte

01 = 32 byte (default)

10 = 64 byte

3:2

TC1DBS

11 = reserved

EDMA TC1 is intended for high throughput bulk transfers.

TC1 FIFO size is 256 bytes, regardless of Default Burst Size setting.

EDMA TC0 Default Burst Size

00 = 16 byte (default)

01 = 32 byte

10 = 64 byte

1:0

TC0DBS

11 = reserved

EDMA TC0 is intended for short burst transfers with stringent deadlines (e.g., McBSP, McASP).

TC0 FIFO size is 128 bytes, regardless of Default Burst Size setting.

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