 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
TMS320DM6435 датащи(PDF) 73 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM6435 датащи(HTML) 73 Page - Texas Instruments |
|
|
73 / 252 page  www.ti.com TMS320DM6435 Digital Media Processor SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007 Table 3-6. Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b) DEVICE BOOT AND CONFIGURATION PLLC1 CLOCK SETTING AT BOOT PINS DM6435 DMP DSPBOOTADDR BOOT DESCRIPTION(1) (Master/Slave) (DEFAULT)(1) DEVICE PLL CLKDIV1 DOMAIN BOOTMODE[3:0] FREQUENCY MODE(2) (SYSCLK1 DIVIDER) (SYSCLK1) 0000 No Boot (Emulation Boot) Master Bypass /1 CLKIN 0x0010 0000 HPI Boot with PLL 0001 Slave x27 /2 CLKIN x27 / 2 0x0010 0000 Multiplier x27 at boot HPI Boot with PLL 0010 Slave x20 /2 CLKIN x20 / 2 0x0010 0000 Multiplier x20 at boot HPI Boot with PLL 0011 Slave x15 /2 CLKIN x15 / 2 0x0010 0000 Multiplier x15 at boot EMIFA ROM FASTBOOT 0100 with Application Image Master x20 /2 CLKIN x20 / 2 0x0010 000 Script (AIS) I2C Boot 0101 Master x20 /2 CLKIN x20 / 2 0x0010 0000 [FAST MODE](3) 0110 16-bit SPI Boot [McBSP0] Master x20 /2 CLKIN x20 / 2 0x0010 0000 0111 NAND Flash Boot Master x20 /2 CLKIN x20 / 2 0x0010 0000 UART Boot without 1000 Hardware Flow Control Master x20 /2 CLKIN x20 / 2 0x0010 0000 [UART0] EMIFA ROM FASTBOOT 1001 Master x20 /2 CLKIN x20 / 2 0x0010 0000 without AIS 1010 VLYNQ Boot Slave x20 /2 CLKIN x20 / 2 0x0010 0000 1011 Reserved – – – – – 1100 Reserved – – – – – 1101 Reserved – – – – – UART Boot with Hardware 1110 Master x20 /2 CLKIN x20 / 2 0x0010 0000 Flow Control [UART0] 24-bit SPI Boot (McBSP0 + 1111 Master x20 /2 CLKIN x20 / 2 0x0010 0000 GP[97]) (1) For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application code must explicitly enable the cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report (literature number SPRAAG0). (2) The PLL MODE for Fixed-Multiplier Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no effect on the PLL MODE. (3) I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not available for MXI/CLKIN frequencies less than 21 MHz. Submit Documentation Feedback Device Configuration 73 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
