PCAL9722HNMP datasheet(29/63 Pages) NXP

29 / 63 page

NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

7.5 Read Access Sequence

In read operation, the registers are read using the following read sequence (from a bus idle condition) as shown

in Figure 12.

1. Drive CS low. This enables the internal shift register.

2. Shift 24 bits of data into the device in a MSB first fashion. Data must be stable during the rising edge of

SCLK

3. The first 7-bit is set for slave address and the 8th bit of the first byte data must be a '1' indicating it is a read

only transfer.

4. The second 8 bits of data should be the address of the register that is intended to read.

5. The third data byte is NOP (no operation) which is dummy data byte (don't care).

6. The read data is shifted out on SDOUT starting from dummy data byte when SCLK is continuously running

from SPI master.

7. After the last bit of data is transferred, drive SCLK low if there is no more data to be transferred.

8. De-assert CS (drive it high) to end of read cycle.

aaa-015970

SCLK

0 1 2 3 4 5 6 7

SDIN

SDOUT

Slave Address

R/W

Reg Address

NOP (don't care)

Read Data (≥ 1 byte)

Figure 12. Read access

7.6 System configuration

A device generating a message is a 'transmitter'; a device receiving is the 'receiver'. The device that controls

the message is the 'master' and the devices which are controlled by the master are the 'slaves' as shown in

Figure 13, two PCAL9722 slave devices can be interfaced to a common SPI bus by connecting SDIN inputs

together, connecting SCLK inputs together, connecting CS inputs together, and connecting SDOUT outputs

together to a micro-controller master device. Each PCAL9722 device has address selection input pin ADDR to

set the slave address.

aaa-015971

MCU

SPI

MASTER

PCAL9722

MISO

MOSI

SDIN

VSS

SDOUT

ADDR

SCLK

PCAL9722

SDIN

VDD

SDOUT

ADDR

SCLK

Figure 13. System level configuration

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

29 / 63

PCAL9722HNMP датащи(PDF) 29 Page - NXP Semiconductors

PCAL9722HNMP датащи(HTML) 29 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL