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SCI Initialization

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-7

Operation starts as follows:

For an internally-generated clock, the SCLK signal starts operation immediately after the

SCI is enabled (Step 3 above) for Asynchronous modes. In Synchronous mode, the SCLK

signal is active only while transmitting (that is, a gated clock).

Data is received only when the receiver is enabled (RE = 1) and after the occurrence of the

SCI receive sequence on the RXD signal, as defined by the operating mode (that is, idle line

sequence).

Data is transmitted only after the transmitter is enabled (TE = 1), and after the

initialization sequence has been transmitted (depending on the operating mode).

8.4.1 Preamble, Break, and Data Transmission Priority

Two or three transmission commands can be set simultaneously:

A preamble (TE is set.)

A break (SBK is set or is cleared.)

An indication that there is data for transmission (TDRE is cleared.)

After the current character transmission, if two or more of these commands are set, the

transmitter executes them in the following order: preamble, break, data.

8.4.2 Bootstrap Loading Through the SCI (Boot Mode $2 or RA)

When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins and

sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits are

write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI.

Appendix A‚ Bootstrap Program shows the complete bootstrap code. This program performs

the following steps:

Configures the SCI.

Loads the program size.

Loads the location where the program begins loading in program memory.

Loads the program.

First, the SCI Control Register is set to $000302, which enables the transmitter and receiver and

configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit, and no

parity. Next, the SCI Clock Control Register is set to $00C000, which configures the SCI to use

external receive and transmit clocks from the SCLK pin input. This external clock must be 16

times the desired serial data rate.

The next step is to receive the program size and then the starting address to load the program.

These two numbers are three bytes each loaded least significant byte first. Each byte is echoed

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