DSP56303 datasheet(173/292 Pages) FREESCALE

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SCI After Reset

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-5

causing the SCI Status Register (SSR) to be reset. No other SCI registers are affected by

the STOP instruction.

Table 8-1 illustrates how each type of reset affects each register in the SCI.

Table 8-1. SCI Registers After Reset

Bit Mnemonic

Bit Number

Reset Type

HW Reset

SW Reset

IR Reset

ST Reset

SCR

REIE

—

SCKP

—

STIR

—

TMIE

—

TIE

—

RIE

—

ILIE

—

WOMS

—

RWU

—

WAKE

—

SBK

—

SSFTD

—

WDS[2–0]

2–0

—

SSR

IDLE

RDRF

TDRE

TRNE

TCM

—

RCM

—

SCCR

SCP

—

COD

—

CD[11–0]

11–0

—

SRX

SRX[23–0]

23–16, 15–8, 7–0

—

STX

STX[23–0]

23–0

—

SRSH

SRS[8–0]

8–0

—

STSH

STS[8–0]

8–0

—

–

SRSH

SCI receive shift register, STSH—SCI transmit shift register

Hardware reset is caused by asserting the external RESET signal.

Software reset is caused by executing the RESET instruction.

Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO).

Stop reset is caused by executing the STOP instruction.

The bit is set during this reset.

The bit is cleared during this reset.

—

The bit is not changed during this reset.

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