DSP56303 datasheet(42/292 Pages) FREESCALE

42 / 292 page

DSP56303 User’s Manual, Rev. 2

2-18

Freescale Semiconductor

Signals/Connections

2.12 JTAG/OnCE Interface

TIO1

Input or

Output

Input

Disconnected

internally

Timer 1 Schmitt-Trigger Input/Output

As an external event counter or in Measurement mode, TIO1 is

input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is

output. The default mode after reset is GPIO input. This can be

changed to output or configured as a Timer Input/Output through

the Timer 1 Control/Status Register (TCSR1). This input is 5 V

tolerant.

TIO2

Input or

Output

Input

Disconnected

internally

Timer 2 Schmitt-Trigger Input/Output

As an external event counter or in Measurement mode, TIO2 is

input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is

output. The default mode after reset is GPIO input. This can be

changed to output or configured as a Timer Input/Output through

the Timer 2 Control/Status Register (TCSR2). This input is 5 V

tolerant.

Notes: 1.

The Wait processing state does not affect the signal state.

Table 2-16. JTAG/OnCE Interface

Signal Name

Type

State During

Reset

Signal Description

TCK

Input

Test Clock

A test clock signal for synchronizing JTAG test logic. This input is 5

V tolerant.

TDI

Input

Test Data Input

A test data serial signal for test instructions and data. TDI is

sampled on the rising edge of TCK and has an internal pull-up

resistor. This input is 5 V tolerant.

TDO

Output

Tri-stated

Test Data Output

A test data serial signal for test instructions and data. TDO can be

tri-stated. The signal is actively driven in the shift-IR and shift-DR

controller states and changes on the falling edge of TCK. This pin is

5 V tolerant.

TMS

Input

Test Mode Select

Sequences the test controller’s state machine, is sampled on the

rising edge of TCK, and has an internal pull-up resistor. This input is

5 V tolerant.

TRST

Input

Test Reset

Asynchronously initializes the test controller, has an internal pull-up

resistor, and must be asserted after power up. This input is 5 V

tolerant.

Table 2-15. Triple Timer Signals (Continued)

Signal

Name

Type

State During1

Reset

Stop

Signal Description

DSP56303 датащи(PDF) 42 Page - Freescale Semiconductor, Inc

DSP56303 датащи(HTML) 42 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL