DSP56303 datasheet(124/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

6-24

Freescale Semiconductor

Host Interface (HI08)

6.7.2 Command Vector Register (CVR)

The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56303 to execute

an interrupt. The host command feature is independent of any of the data transfer mechanisms in

the HI08. It causes execution of any of the 128 possible interrupt routines in the DSP core.

Hardware, software, individual, and stop resets clear the CVR bits.

6.7.3 Interface Status Register (ISR)

The host processor uses the ISR, an 8-bit read-only status register, to interrogate the HI08 status

and flags. The DSP core cannot address the ISR.

76543210

HV6

HV5

HV4

HV3

HV2

HV1

HV0

Figure 6-16. Command Vector Register (CVR)

Table 6-16. Command Vector Register (CVR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

7HC

Host Command

The host processor uses the HC bit to handshake the execution of host

command interrupts. Normally, the host processor sets HC to request a

host command interrupt from the DSP56303. When the DSP56303

acknowledges the host command interrupt, HI08 hardware clears the

HC bit. The host processor can read the state of HC to determine when

the host command has been accepted. After setting HC, the host must

not write to the CVR again until the HI08 hardware clears the HC. Setting

the HC bit causes host command pending (HCP) to be set in the HSR.

The host can write to the HC and HV bits in the same write cycle.

6–0

HV[6–0]

$32

Host Vector

Select the host command interrupt address for use by the host command

interrupt logic. When the DSP interrupt control logic recognizes the host

command interrupt, the address of the interrupt routine taken is 2

× HV.

The host can write HC and HV in the same write cycle.

The host processor can select any of the 128 possible interrupt routine

starting addresses in the DSP by writing the interrupt routine address

divided by 2 into the HV bits. This means that the host processor can

force any interrupt handler (ESSI, SCI, IRQA, IRQB, and so forth) and

can use any reserved or otherwise unused addresses (if have been

pre-programmed in the DSP). HV is set to $32 (vector location $064) by

hardware, software, individual, and stop resets.

76543210

HREQ

HF3

HF2

TRDY

TXDE

RXDF

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 6-17. Interface Status Register (ISR)

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