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Monolithic Transistor Array – SiS3045

Rev 1.1

20/10/17

1020µm (40 mils)

PAD

FUNCTION

1

COLLECTOR Q1

2

BASE Q1

3

EMITTERS Q1 & Q2

4

BASE Q2

5

COLLECTOR Q2

6

BASE Q3

7

EMITTER Q3

8

COLLECTOR Q3

9

BASE Q4

10

EMITTER Q4

11

COLLECTOR Q4

12

BASE Q5

13

EMITTER Q5 & SUBSTRATE

14

COLLECTOR Q5

 

Pad Layout and Functions

Circuit Schematic

Q5

Q4

Q1

Q2

Q3

14

13

12

11

10

9

8

1

2

3

4

5

6

7

Die backside must be connected to the most negative point in the external circuit to maintain isolation between

transistors and to provide for normal transistor action.

 

9

8

7

6

5

4

3

2

1

10

11

12

13

14