Monolithic Transistor Array – SiS3045  

Silicon General Purpose x5 NPN Transistor array in bare die form

Rev 1.1

20/10/17

Two matched transistors:

-

VBE Match ±5mA

-

IIO Match 2µA (Max).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1020 x 1020

40 x 40

µm

mils

Minimum Bond Pad Size

100 x 100

4 x 4

µm

mils

Die Thickness

460

18.1

µm

mils

Top Metal Composition

TiW-AlSi 0.15µm-3µm

Back Metal Composition

N/A – Bare Si

Low Noise Figure 3.2dB (Typ) at 1kHz

Operation From DC to 120MHz

Wide Operating Current Range

Full Military Temperature Range.

Features:

The SiS3045 consists of five general purpose silicon NPN

transistors on a common monolithic substrate. Two of the

transistors are internally connected to form a differentially-

connected pair. The transistors are well suited to a wide

variety of applications in low power systems in the DC

through VHF range. They may be used as discrete

transistors in conventional circuits however; in addition, they

provide the very significant inherent integrated circuit

advantages of close electrical and thermal matching. The

SiS3045 is a direct electrical & mechanical replacement for

the obsolete Intersil CA3045 & National (TI) LM3045.

Description

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

1020 (40)

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – By specific request

Unsawn Wafer – By specific request

14 Lead CERDIP / PDIP package – By specific request

14 Lead SOIC package – By specific request

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