ST10F273 datasheet(149/179 Pages) STMICROELECTRONICS

149 / 179 page

ST10F273

Electrical characteristics

149/179

Example 1

●

FXTAL = 4 MHz

●

P0(15:13) = ‘110’ (multiplication by 3)

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PLL input frequency = 1 MHz

●

VCO frequency = 48 MHz

●

PLL output frequency = 12 MHz

(VCO frequency divided by 4)

●

FCPU = 12 MHz (no effect of Output Prescaler)

Example 2

●

FXTAL = 8 MHz

●

P0(15:13) = ‘100’ (multiplication by 5)

●

PLL input frequency = 2 MHz

●

VCO frequency = 80 MHz

●

PLL output frequency = 40 MHz (VCO frequency divided by 2)

●

FCPU = 40 MHz (no effect of Output Prescaler)

24.8.9

PLL jitter

The following terminology is hereafter defined:

●

Self referred single period jitter

Also called “Period Jitter”, it can be defined as the difference of the Tmax and Tmin,

where Tmax is maximum time period of the PLL output clock and Tmin is the minimum

time period of the PLL output clock.

●

Self referred long term jitter

Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where

Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the

minimum time difference between N+1 clock rising edges. Here N should be kept

sufficiently large to have the long term jitter. For N=1, this becomes the single period

jitter.

Jitter at the PLL output can be due to the following reasons:

●

Jitter in the input clock

●

Noise in the PLL loop

Jitter in the input clock

PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the

frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency

jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.

Noise in the PLL loop

This contribution again can be caused by the following sources:

●

Device noise of the circuit in the PLL

●

Noise in supply and substrate.

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