ST10F273 datasheet(147/179 Pages) STMICROELECTRONICS

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ST10F273

Electrical characteristics

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24.8.5

Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is

disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by

the input clock signal on XTAL1 pin.

The frequency of CPU clock (fCPU) directly follows the frequency of fXTAL so the high and

low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the

input clock fXTAL.

Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value

can be calculated by the following formula:

For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,

so the duration of 2TCL is always 1/fXTAL.

The minimum value TCLmin has to be used only once for timings that require an odd number

of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:

The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of

TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLMin.

Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is

cleared, the PLL runs on its free-running frequency and delivers the clock signal for the

Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.

24.8.6

Oscillator watchdog (OWD)

An on-chip watchdog oscillator is implemented in the ST10F273. This feature is used for

safety operation with external crystal oscillator (available only when using direct drive mode

with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the

frequency of the external crystal oscillator). This watchdog oscillator operates as following.

The reset default configuration enables the watchdog oscillator. It can be disabled by setting

the OWDDIS (bit 4) of SYSCON register.

When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the

watchdog counter. On each transition of external clock, the watchdog counter is cleared. If

an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock

cycles).

The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator

watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external

clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or

bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct

clock input.

When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct

Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply

current.

TCL

min

⁄

XTALl

xlDC

min

duty cycle

2TCL

1 f

XTAL

⁄

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