ST10F273 datasheet(148/179 Pages) STMICROELECTRONICS

148 / 179 page

Electrical characteristics

ST10F273

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24.8.7

Phase locked loop (PLL)

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked

loop is enabled and it provides the CPU clock (see Table 69). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU =

fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to

the input clock. This synchronization is done smoothly, so the CPU clock frequency does not

change abruptly.

Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of

individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated

using the minimum TCL that is possible under the respective circumstances.

The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to

keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to

one TCL period.

This is especially important for bus cycles using wait states and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is

negligible. Refer to next Section 24.8.9: PLL jitter for more details.

24.8.8

Voltage controlled oscillator

The ST10F273 implements a PLL which combines different levels of frequency dividers with

a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table,

a detailed summary of the internal settings and VCO frequency is reported.

The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is

64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.

Table 70.

Internal PLL divider mechanism

P0.15-13

(P0H.7-5)

XTAL frequency

Input

prescaler

PLL

Output

prescaler

CPU frequency

fCPU = fXTAL x F

Multiply

Divide by

4 to 8 MHz

FXTAL / 4

–

FXTAL x 4

5.3 to 10.6 MHz

FXTAL x 3

4 to 8 MHz

FXTAL x 8

6.4 to 12 MHz

FXTAL x 5

1 to 64 MHz

–

PLL bypassed

FXTAL x 1

4 to 6.4MHz

FXTAL / 2

–

FXTAL x 10

4 to 12MHz1)

–

PLL bypassed

FPLL / 2

FXTAL / 2

000

4MHz

FXTAL / 2

–

FXTAL x 16

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