HT86R192 datasheet(19/44 Pages) HOLTEK

19 / 44 page

HT86R192

Rev. 0.00

October 23, 2006

Preliminary

Timer Counter 2

The timer counter TMR2 is also a 16-bit programmable

count-up counter. It operates in the same manner as

Timer/Event Counter 0/1, but the clock source of TMR2

is from only internal instruction cycle (T1). Therefore

only (TM1,TM0)=(1,0) is allowable.

Timer Counter 3 (RTC Time Base)

The timer counter TMR3 is an 8-bit programmable

count-up counter. Its counting is as the same manner as

Timer Event Counter 0/1 and Timer Counter 2, but the

clock source of TMR3 can be from internal instruction

cycle (T1) or external 32kHz crystal which is connected

to XIN and XOUT. The TMR3

¢s clock source is deter-

mined by OTP option. If the 32kHz crystal is enabled,

then TMR3

¢s clock source is 32kHz which is from XIN

and XOUT. If the 32kHz crystal is disabled, then TMR3

¢s

clock source is internal T1.

The TMR3 is internal clock source only, i.e.

(TM1,TM0)=(1,0). There is a 3-bit prescaler

(TMR3S2,TMR3S1,TMR3S0) which defines different

division ratio of TMR3

¢s clock source.

S y s t e m C l o c k / 4

T M 1

T M 0

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r 2

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r 2

L o w B y t e

B u f f e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

G N D

Timer Counter 2

S y s t e m C l o c k / 4

8 - S t a g e

P r e s c a l e r

T i m e r C o u n t e r 3

P r e l o a d R e g i s t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

T i m e r C o u n t e r 3

T O N

M a s k

O p t i o n

3 2 K C r y s t a l

( T M R 3 S 2 , T M R 3 S 1 , T M R 3 S 0 )

Timer Counter 3

Bit No.

Label

Function

0~2

TMR3S2,

TMR3S1,

TMR3S0

To define the operating clock source (TMR3S2, TMR3S1, TMR3S0)

000: clock source/2

001: clock source/4

010: clock source/8

011: clock source/16

100: clock source/32

101: clock source/64

110: clock source/128

111: clock source/256

3TE

To define the TMR3 active edge of timer/event counter

(0=active on low to high; 1=active on high to low)

TON

To enable/disable timer counting (0=disabled; 1=enabled)

Unused bit, read as

²0²

TM0,

TM1

To define the operating mode (TM1, TM0)

01=Unused

10=Timer mode (internal clock)

11=Unused

00=Unused

TMR3C (25H) Register

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