HT86R192 datasheet(17/44 Pages) HOLTEK

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HT86R192

Rev. 0.00

October 23, 2006

Preliminary

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses after a system

power up or when awakening from a HALT state.

When a system power up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

The function unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

Input/output ports

Input mode

Stack Pointer

Points to the top of the stack

Timer/Event Counter 0/1

There are four timer counters are implemented in the

HT86R192. The Timer/Event Counter 0 and 1 contain

16-bit programmable count-up counters whose clock

may come from an external source or the system clock

divided by 4 (T1). Using the internal instruction clock

(T1), there is only one reference time base. The external

clock input allows the user to count external events,

measure time intervals or pulse width, or to generate an

accurate time base.

There are three registers related to Timer/Event Counter

0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing

to TMR0L only writes the data into a low byte buffer. Writ-

ing to TMR0H will write the data and the contents of the

low byte buffer into the Timer/Event Counter 0 preload

ter 0 preload register is changed only by a write to

TMR0H operation. Writing to TMR0L will keep the

Timer/Event Counter 0 preload register unchanged.

Reading TMR0H will also latch the TMR0L into the low

byte buffer to avoid false timing problems. Reading the

TMR0L only returns the value from the low byte buffer

which may be a previously loaded value. In other words,

the low byte of Timer/Event Counter 0 cannot be read di-

rectly. It must read the TMR0H first to ensure that the

low byte contents of Timer/Event Counter 0 are latched

into the buffer.

There are three registers related to the Timer/Event

Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).

The Timer/Event Counter 1 operates in the same man-

ner as Timer/Event Counter 0.

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

R E S

V D D

Reset Circuit

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s e t

W a r m R e s e t

P o w e r - o n D e t e c t i n g

S S T

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

Reset Configuration

S y s t e m C l o c k / 4

T M 1

T M 0

T M R 0

T M R 1

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r 0 / 1

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r 0 / 1

L o w B y t e

B u f f e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

Timer/Event Counter 0/1

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