HT46R46E datasheet(22/73 Pages) HOLTEK

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HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E

Rev. 1.20

August 15, 2007

· External Interrupt Input

The external interrupt pin INT is pin-shared with the

I/O pin PA5. For applications not requiring an external

interrupt input, the pin-shared external interrupt pin

can be used as a normal I/O pin, however to do this,

the external interrupt enable bits in the INTC register

must be disabled.

· External Timer Clock Input

The external timer pin TMR is pin-shared with the I/O

pin PA4. To configure it to operate as a timer input, the

corresponding control bits in the timer control register

must be correctly set. For applications that do not re-

quire an external timer input, the pin can be used as a

normal I/O pin. Note that if used as a normal I/O pin

the timer mode control bits in the timer control register

must select the timer mode, which has an internal

clock source, to prevent the input pin from interfering

with the timer operation.

· PFD Output

Each device contains a PFD function whose single

output is pin-shared with PA3. The output function of

this pin is chosen via a configuration option and re-

mains fixed after the device is programmed. Note that

the corresponding bit of the port control register,

PAC.3, must setup the pin as an output to enable the

PFD output. If the PAC port control register has setup

the pin as an input, then the pin will function as a nor-

mal logic input with the usual pull-high option, even if

the PFD configuration option has been selected.

· PWM Outputs

All devices contain one or two PWM outputs pin

shared with pins PD0 and PD1. The PWM output

functions are chosen via configuration options and re-

main fixed after the device is programmed. Note that

the corresponding bit or bits of the port control regis-

ter, PDC, must setup the pin as an output to enable

the PWM output. If the PDC port control register has

setup the pin as an input, then the pin will function as a

normal logic input with the usual pull-high option, even

if the PWM configuration option has been selected.

· A/D Inputs

Each device has four A/D converter inputs. All of

these analog inputs are pin-shared with I/O pins on

Port B. If these pins are to be used as A/D inputs and

not as normal I/O pins then the corresponding bits in

the A/D Converter Control Register, ADCR, must be

properly set. There are no configuration options asso-

ciated with the A/D function. If used as I/O pins, then

full pull-high resistor configuration options remain,

however if used as A/D inputs then any pull-high resis-

tor options associated with these pins will be automat-

ically disconnected.

· SCL/SDA EEPROM Pins

The internal EEPROM has two active pins, a clock

pin, SCL, and a data pin, SDA. The SDA pin is shared

with pin PD0 on the HT46R46E and HT46R47E de-

vices and with pin PC0 on the other devices. The SCL

pin is shared with pin PB3 on the HT46R46E and

HT46R47E devices and with pin PC1 on the other de-

vices. Data can be transmitted to and from the

EEPROM using their corresponding I/O shared pins.

The EEPROM pins, SCL and SDA, can also be con-

nected to an external I

2C bus, allowing it to be con-

trolled by an external I

2C master device. In this case

the I/O pins must be setup as inputs. Care must also

be taken if these pins are used as normal I/O pins as

the internal EEPROM may interpret regular I/O pin

data as EEPROM read or write commands, which

could result in unexpected programming errors. Note

that there is no configuration option associated with

these shared pins.

I/O Pin Structures

The following diagrams illustrate the I/O pin internal

structures. As the exact logical construction of the I/O

pin may differ from these drawings, they are supplied as

a guide only to assist with the functional understanding

of the I/O pins.

V D D

W a k e - u p O p t i o n

S y s t e m W a k e - u p

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - H i g h

O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

I / O P i n

W e a k

P u l l - u p

C K

P A o n l y

Non-pin-shared Function Input/Output Ports

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