HT46R46E datasheet(20/73 Pages) HOLTEK

20 / 73 page

HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E

Rev. 1.20

August 15, 2007

Write Operations

There is only one write operation which is a byte write.

· Byte Write

A byte write operation allows a single byte of data to

be written into the EEPROM. For this to happen, a

start condition, device address and read/write bit must

first be transmitted. Then after the usual acknowledge

signal is received from the EEPROM, the required

EEPROM internal address information where the data

is to be written must be transmitted. In this case, as an

address is being written to the EEPROM, the

read/write bit should be low. After the 8-bit address

has been transmitted in an MSB format, the EEPROM

will respond with another acknowledge signal. At this

point the internal counter is now pointing to the re-

quested address. Now the 8-bits of data to be written,

in an MSB format, can be transmitted to the

EEPROM. When the last bit has been received the

EEPROM will respond with the usual acknowledge

signal, after which a STOP condition should be trans-

mitted to the EEPROM. After the EEPROM receives

the STOP condition it will enter its internal write cycle.

The internal write cycle is fully controlled and timed by

the EEPROM and when running, no other EEPROM

operations can be executed.

· Internal Write Cycle

After a write operation is executed and when the

EEPROM receives the final STOP condition at the

end of the write operation, it will enter its internally

controlled and timed internal write cycle. When the in-

ternal write cycle is executing, no other operations can

be carried out on the EEPROM. Before executing fur-

ther operations on the EEPROM, therefore, a time de-

lay must be provided, whose value should be equal to

the maximum write cycle time, tWR, as specified in the

EEPROM A.C. Characteristics table. However as only

a maximum time is provided, a better method, using

polling to determine when the write cycle has finished,

can be used. To do this a START condition, followed

by a device address and read/write bit low, is transmit-

ted to the EEPROM. If the write cycle has completed

the EEPROM will respond with an acknowledge sig-

nal, which means the SDA line will be pulled low. If the

write cycle has not completed then no acknowledge

signal will be generated and the SDA line will remain

high.

D e v i c e a d d r e s s

W o r d a d d r e s s

D a t a

S D A

S t a r t

A c k n o w l e d g e f r o m E E P R O M - - S D A p u l l e d l o w

R / W l o w

- - W r i t e

S t o p

Byte Write

S e n d W r i t e C o m m a n d

S e n d S t o p C o n d i t i o n

t o I n i t i a t e I n t e r n a l

W r i t e C y c l e

S e n d S t a r t

S e n d D e v i c e A d d r e s s

R / W = 0

A c k n o w l e d g e

R e c e i v e d

N e x t O p e r a t i o n

N o

Y e s

S D A = 0

I n t e r n a l w r i t e c y c l e

s t i l l r u n n i n g

Internal Write Cycle Busy Polling

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