HT36B2 datasheet(10/39 Pages) HOLTEK

10 / 39 page

HT36B2

Rev. 1.10

March 10, 2005

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt needs servicing within the service routine, the pro-

grammer may set the EMI bit and the corresponding bit

of the INTC to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if

the related interrupt is enabled, until the SP is decre-

mented. If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupt have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack and then

branching to subroutines at specified locations in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register and Status

program which may corrupt the desired control se-

quence, then the programmer must save the contents

first.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F;bit 5 of the INTC), caused by a

Timer/Event Counter 0 overflow. When the interrupt is

enabled, and the stack is not full and the T0F bit is set, a

subroutine call to location 08H will occur. The related in-

terrupt request flag (T0F) will be reset and the EMI bit

cleared to disable further interrupts.

The Timer/Event Counter 1 interrupt is operated in the

same manner as Timer/Event Counter 0. The related in-

terrupt control bits ET1I and T1F of the Timer/Event

Counter 1 are bit 3 and bit 6 of the INTC respectively.

External interrupt is initialized by setting the external re-

quest flag (EEI; bit 1 of the INTC), caused by a high-to

low voltage pulse from the INT pad. When the interrupt

is enabled, and the stack is not full and the EEI bit is set,

a subroutine call to location 04H will occur. The related

interrupt request flag (EIF) will be reset and the EMI bit

cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt

04H

Timer/event Counter 0 overflow

08H

Timer/event Counter 1 overflow

0CH

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F), Enable Timer/Event Counter 0/1 bit

(ET0I/ET1I), Enable Master Interrupt bit (EMI) consti-

tute an interrupt control register (INTC) which is located

at 0BH in the data memory. EMI, ET0I, ET1I are used to

control the enabling/disabling of interrupts. These bits

prevent the requested interrupt from being serviced.

Once the interrupt request flags (T0F, T1F) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Be-

cause interrupts often occur in an unpredictable manner

or need to be serviced immediately in some applica-

tions, if only one stack is left and enabling the interrupt is

not well controlled, once the

²CALL subroutine² operates

in the interrupt subroutine, it may damage the original

control sequence.

Oscillator Configuration

The HT36B2 provides two types of oscillator circuit for

the system clock, i.e., RC oscillator and crystal oscilla-

tor. No matter what type of oscillator, the signal divided

by 2 is used for the system clock. The HALT mode stops

the system oscillator and ignores external signal to con-

serve power. If the RC oscillator is used, an external re-

sistor between OSC1 and VSS is required, and the

range of the resistance should be from 30k

W to 680kW.

The system clock, divided by 4, is available on OSC2

with pull-high resistor, which can be used to synchronize

external logic. The RC oscillator provides the most cost

effective solution. However, the frequency of the oscilla-

tion may vary with VDD, temperature, and the chip itself

due to process variations. It is therefore, not suitable for

timing sensitive operations where accurate oscillator

frequency is desired.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 8

O S C 1

V D D

System Oscillator

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