AD9984A datasheet(33/44 Pages) AD

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AD9984A

Rev. 0 | Page 33 of 44

0x14—Bit[1] Vsync Duration Block Enable

This enables the Vsync duration block, which is designed to be

used with the Vsync filter. Setting the bit to 0 leaves the Vsync

output duration unchanged. Setting the bit to 1 sets the Vsync

output duration based on Register 0x15. Power-up duration is 0.

Table 29. Vsync Duration Block Enable Bit

Value

Result

Vsync output duration is unchanged.

Vsync output duration is set by Register 0x15.

0x15—Bits[7:0] Vsync Duration

This register is used to set the output duration of the Vsync, and

is designed to be used with the Vsync filter. This is valid only if

COAST AND CLAMP CONTROLS

0x16—Bits[7:0] Precoast

This register allows the internally generated coast signal to be

applied prior to the Vsync signal. This is necessary in cases

where pre-equalization pulses are present. The step size for this

control is one Hsync period. For precoast to work correctly, it is

necessary for both the Vsync filter (Register 0x14, Bit 2) and

sync processing filter (Register 0x20, Bit 1) to either be enabled

or disabled. The power-up default is 00.

0x17—Bits[7:0] Postcoast

This register allows the internally generated coast signal to be

applied following the Vsync signal. This is necessary in cases

where post equalization pulses are present. The step size for this

control is one Hsync period. For postcoast to work correctly, it

is necessary for both the Vsync filter (Register 0x14, Bit 2) and

sync processing filter (Register 0x20, Bit 1) to be enabled or

disabled. The power-up default is 00.

0x18—Bit[7] Coast Source

This bit is used to select the active coast source. The choices are

the COAST input pin or Vsync. If Vsync is selected, the addi-

tional decision of using the VSYNCx input pin or the output from

the sync separator needs to be made (Register 0x14, Bits[7:6]).

Table 30. Coast Source Bit

Value

Result

Vsync (internal coast).

COAST pin.

0x18—Bit[6] Coast Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into the PLL.

The power-up default setting is 0.

Table 31. Coast Polarity Override Bit

Value

Result

Coast polarity determined by chip.

Coast polarity determined by user (Register 0x18, Bit 5).

0x18—Bit[5] Input Coast Polarity

This register sets the input coast polarity when Bit 6 of Register

0x18 is 1. The power-up default setting is 1.

Table 32. Input Coast Polarity Bit

Value

Result

Coast polarity is negative.

Coast polarity is positive.

0x18—Bit[4] Clamp Source Select

This bit determines the source of clamp timing. A 0 enables the

clamp timing circuitry controlled by clamp placement and

clamp duration. The clamp position and duration is counted

from the leading edge of Hsync. A 1 enables the external

CLAMP input pin. The three channels are clamped when the

clamp signal is active. The polarity of clamp is determined by

the CLAMP polarity bit. The power-up default setting is 0.

Table 33. Clamp Source Select Bit

Value

Result

Internally generated clamp.

Externally provided clamp signal (CLAMP).

0x18—Bit[3] Red Clamp Select

This bit determines whether the red channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 34. Red Clamp Select Bit

Value

Result

Clamp to ground.

Clamp to midscale.

0x18—Bit[2] Green Clamp Select

This bit determines whether the green channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 35. Green Clamp Select Bit

Value

Result

Clamp to ground.

Clamp to midscale.

0x18—Bit[1] Blue Clamp Select

This bit determines whether the blue channel is clamped to

ground or to midscale. The power-up default setting is 0.

Table 36. Blue Clamp Select Bit

Value

Result

Clamp to ground.

Clamp to midscale.

0x18—Bit[0]

Must be set to 0 for proper operation.

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