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AD9984A датащи(PDF) 39 Page - Analog Devices

номер детали AD9984A
подробное описание детали  High Performance 10-Bit Display Interface
PDF  44 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9984A датащи(HTML) 39 Page - Analog Devices

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AD9984A
Rev. 0 | Page 39 of 44
0x2E—Bits[7:0] Test Register 6
Read/write bits for future use. Must be written to 0xE0 for
proper operation.
0x34—Bit[2] SOG Filter Enabler
When this bit is set to 1, the SOG does not pass pulses less than
250 ns in width. This reduces spurious signals that can improperly
drive the PLL circuit. Default for this bit is 0 or off.
0x36—Bit[0] VCO Gear Select
This bit allows the VCO to select a lower gear to run lower pixel
clocks while remaining in a more linear range.
Table 78. VCO Gear Select Bit
Value
Result
0
Normal VCO setting.
1
Enables lower VCO clock output.
0x3C—Bits[7:4] Test Bits
Must be set to 0x0 for proper operation.
0x3C—Bit[3] Auto Gain Matching Hold
This bit controls whether the auto gain matching function runs
continuously or runs once and holds the result. Continuous
updates are recommended because they allow the AD9984A to
compensate for drift over time, temperature, and so on.
If one-time updates are preferred, they should be performed
every time the part is powered up and when there is a mode
change. To perform a one-time update, auto gain matching
must first be enabled (Register 0x3C, Bits[2:0]). Next, this bit
(auto gain matching hold) must first be set to 1 to let the auto
gain matching function operate and settle to a final value.
The auto gain matching hold bit should then be set to 0 to hold
the gain values that the auto circuitry calculates. The AD9984A
auto gain matching circuit’s maximum settle time is 10 updates.
For example, if the update frequency is set to once every 64 Hsyncs,
the maximum settling time would be 640 Hsyncs (10 × 64 Hsyncs).
Table 79. Auto Gain Matching Hold Bit
Value
Result
01
Disables auto gain updates and holds the current
auto gain values.
1
Allows auto gain to update continuously.
1The power-up default setting is 0.
0x3C—Bits[2:0] Auto Gain Matching Enable
These bits enable or disable the auto gain matching function.
Table 80. Auto Gain Matching Enable Bits
Value
Result
000
Auto gain matching disabled.
110
Auto gain matching enabled.



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