405EX datasheet(43/67 Pages) AMCC

43 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

SVREF1A:B

SVREF2A:B

DDR 1 (DDR2) Reference voltage 1 and 2 inputs:

Min. +1.15 (+0.825)V

Nom. +1.25 (+0.9)V

Max. +1.35 (0.975)V

1.25V (0.9V)

Volt ref receiver

Serial Communication Port (SCP) Interface

SCPClkOut

Output clock.

I/O

3.3V LVTTL

SCPDI

Data input.

3.3V LVTTL

SCPDO

Data output.

3.3V LVTTL

UART Peripheral Interface

The UART interface can be configured as follows:

1. One 8-pin

2. Two 4-pin

3. Two 2-pin (pull up DCD, DSR, CTS and RTS)

4. One 4-pin and one 2-pin

UARTSerClk

Serial clock input.

3.3V LVTTL

receiver

w/pull-up

UARTnCTS

Clear to send.

I/O

3.3V LVTTL

1, 6

UARTnDCD

Data carrier detect.

I/O

3.3V LVTTL

1, 6

UARTnDSR

Data set ready.

I/O

3.3V LVTTL

1, 6

UARTnDTR

Data terminal ready.

I/O

3.3V LVTTL

UARTnRI

Ring indicator.

I/O

3.3V LVTTL

UARTnRTS

Request to send.

I/O

3.3V LVTTL

UARTnRx

Receive data.

3.3V LVTTL

receiver

w/pull-down

UARTnTx

Transmit data.

3.3V LVTTL

USB 2.0 Interface

USB2Clk

USB clock.

3.3V LVTTL

receiver

USB2Data0:7

Parallel data bus.

I/O

3.3V LVTTL

USB2Dir

Data bus direction control.

I/O

3.3V LVTTL

USB2Next

Next data byte control. When data is being transferred to the PHY,

the next byte should be sent. When data is being received from the

PHY, the next byte is available.

I/O

3.3V LVTTL

USB2Stop

Stop output control.

I/O

3.3V LVTTL

Table 6. Signal Functional Description (Sheet 6 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

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