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C8051F360 датащи(PDF) 65 Page - Silicon Laboratories

номер детали C8051F360
подробное описание детали  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 датащи(HTML) 65 Page - Silicon Laboratories

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Rev. 1.0
65
C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 6.1. IDA0CN: IDA0 Control
Bit 7:
IDA0EN: IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0H. (default)
Bits 3–2: UNUSED. Read = 00b. Write = don’t care.
Bits 1–0: IDA0OMD[1:0]: IDA0 Output Mode Select bits.
00: 0.5 mA full-scale output current.
01: 1.0 mA full-scale output current.
1x: 2.0 mA full-scale output current. (default)
SFR Page:
SFR Address:
all pages
0xB9
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Reset Value
IDA0EN
IDA0CM
––
IDA0OMD
01110010
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Definition 6.2. IDA0H: IDA0 Data Word MSB
Bits 7–0: IDA0 Data Word High-Order Bits.
Bits 7–0 are the most-significant bits of the 10-bit IDA0 Data Word.
SFR Page:
SFR Address:
all pages
0x97
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0



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