PM7367 datasheet(136/323 Pages) PMC

136 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

122

CEN:

The channelise enable bit (CEN) configures receive link #3 for channelised

operation. RCLK[3] is held quiescent during the T1 framing bit and the E1

framing bytes. The data bit on RD[3] clocked in by the first rising edge of

RCLK[3] after an extended quiescent period is considered to be the most

significant bit of time-slot 1. When CEN is set low, the corresponding receive

link is unchannelised. The E1 register bit is ignored. RCLK[3] is gapped

during non-data bytes. All data bits are treated as a contiguous stream with

arbitrary byte alignment.

E1:

The E1 frame structure select bit (E1) configures receive link #3 for

channelised E1 operation when CEN is set high. RCLK[3] is held quiescent

during the FAS and NFAS framing bytes. The data bit on RD[3] clocked in by

the first rising edge of RCLK[3] after an extended quiescent period is

considered to be the most significant bit of time-slot 1. Link data is present at

time-slots 1 to 31. When E1 is set low and CEN is set high, receive link #3 is

configured for channelised T1 operation. RCLK[3] is held quiescent during

the framing bit. The data bit on RD[3] clocked in by the first rising edge of

RCLK[3] after an extended quiescent period is considered to be the most

significant bit of time-slot 1. Link data is present at time-slots 1 to 24. E1 is

ignored when CEN is set low.

PM7367 датащи(PDF) 136 Page - PMC-Sierra, Inc