PM7367 datasheet(317/323 Pages) PMC

317 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

303

Table 33 – FREEDM-32P32 Link Output (Figure 40, Figure 41)

Symbol

Description

Min

Max

Units

TCLK[31:0] Frequency (See Note 4)

1.542

1.546

MHz

TCLK[31:0] Frequency (See Note 5)

2.046

2.05

MHz

TCLK[2:0] Frequency (See Note 6)

MHz

TCLK[31:3] Frequency (See Note 6)

MHz

TCLK[31:0] Duty Cycle

tPTD

TCLK[2:0] Low to TD[2:0] Valid

tPTD

TCLK[31:3] Low to TD[31:3] Valid

tPRBD

RBCLK Low to RBD Valid

-5

Notes on Output Timing:

1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt

point of the reference signal to the 1.4 Volt point of the output.

2. Maximum and minimum output propagation delays are measured with a 50

pF load on all the outputs, except for PCI Bus outputs and TD[2:0] outputs.

For PCI Bus outputs, maximum output propagation delays are measured with

a 50 pF load while minimum output propagation delays are measured with a

0 pF load. For TD[2:0] outputs, propagation delays are measured with a 20

pF load. Maximum propagation delay for TD[2:0] increases by 1.0 ns for

each 10 pF of extra load.

3. Output propagation delays of signal outputs that are specified in relation to a

reference output are measured with a 50 pF load on both the signal output

and the reference output.

4. Applicable only to channelised T1 links and measured between framing bits.

5. Applicable only to channelised E1 links and measured between framing bytes.

6. Applicable only to unchannelised links of any format and measured between

any two TCLK rising edges.

7. Output tri-state delay is the time in nanoseconds from the 1.4 Volt point of the

reference signal to the point where the total current delivered through the

output is less than or equal to the leakage current.

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