PM7367 datasheet(309/323 Pages) PMC

309 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

295

During clock 3, the target latches in the data element and negates TRDYB and

DEVSELB, having seen FRAMEB negated previously. The initiator negates

IRDYB and drives FRAMEB to start the next cycle. It also drives the address

onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command.

In this example the command would indicate a burst write.

During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus

and starts driving the first data element. The initiator also drives the C/BEB[3:0]

lines with the byte enables for the write data. IRDYB is driven active by the

initiator to indicate that the data is valid. The target claims the transaction by

driving DEVSELB active and drives TRDYB to indicate to the initiator that it is

ready to accept the data.

During clock 5, the initiator is ready to transfer the next data element so it drives

the AD[31:0] lines with the second data element. The initiator negates FRAMEB

since this is the last data phase of this cycle. The target accepts the first data

element and negates TRDYB to indicate its is not ready for the next data

element.

During clock 6, the target is still not ready so a wait state shall be added.

During clock 7, the target asserts TRDYB to indicate that it is ready to complete

the transfer.

During clock 8, the target latches in the last element and negates TRDYB and

DEVSELB, having seen FRAMEB negated previously. The initiator negates

IRDYB. All of the above signals shall be driven to their inactive state in this clock

cycle, except for FRAMEB which shall be tri-stated. The target stops driving the

AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall be the

turnaround cycle for these signals.

PM7367 датащи(PDF) 309 Page - PMC-Sierra, Inc