PM7367 datasheet(220/323 Pages) PMC

220 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

206

FPTR[8:0]:

The indirect FIFO block pointer (FPTR[8:0]) informs the partial packet buffer

processor the circular linked list of blocks to use for a FIFO for the channel.

The FIFO pointer to be written to the channel provision RAM, in an indirect

write operation, must be set up in this register before triggering the write. The

FIFO pointer value can be any one of the block numbers provisioned, by

indirect block write operations, to form the circular buffer.

DELIN:

The indirect delineate enable bit (DELIN) configures the HDLC processor to

perform flag sequence insertion and bit stuffing on the outgoing data stream.

The delineate enable bit to be written to the channel provision RAM, in an

indirect channel write operation, must be set up in this register before

triggering the write. When DELIN is set high, flag sequence insertion, bit

stuffing and ,optionally, CRC generation is performed on the outgoing HDLC

data stream. When DELIN is set low, the HDLC processor does not perform

any processing (flag sequence insertion, bit stuffing nor CRC generation) on

the outgoing stream. DELIN reflects the value written until the completion of

a subsequent indirect channel read operation.

IDLE:

The interframe time fill bit (IDLE) configures the HDLC processor to use flag

bytes or HDLC idle as the interframe time fill between HDLC packets. The

value of IDLE to be written to the channel provision RAM, in an indirect

channel write operation, must be set up in this register before triggering the

write. When IDLE is set low, the HDLC processor uses flag bytes as the

interframe time fill. When IDLE is set high, the HDLC processor uses HDLC

idle (all one's bit with no bit-stuffing pattern is transmitted) as the interframe

time fill. IDLE reflects the value written until the completion of a subsequent

indirect channel read operation.

CRC[1:0]:

The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform

CRC generation on the outgoing HDLC data stream. The value of CRC[1:0]

to be written to the channel provision RAM, in an indirect channel write

operation, must be set up in this register before triggering the write. CRC[1:0]

is ignored when DELIN is low. CRC[1:0] reflects the value written until the

completion of a subsequent indirect channel read operation.

Table 22 – CRC[1:0] Settings

CRC[1]

CRC[0]

Operation

No CRC

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