PM7347 datasheet(73/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously

transmitted at any time by setting a control bit. During packet transmission, an underrun situation

can occur if data is not written to the TDPR Transmit Data Register before the previous byte has

been depleted. In this case, an abort sequence is transmitted, and the controlling processor is

notified by the UDR register bit. An abort sequence will also be transmitted if the user overflows

the FIFO with a packet of length greater than 128 bytes. Overflows where other complete packets

are still stored in the FIFO will not generate an abort. Only the packet which caused the overflow

is corrupted and an interrupt is generated to the user by the OVR register bit. The other packets

remain unaffected.

When the TDPR is disabled, a logic one (Idle) is inserted in the PMDL.

10.18 SPLT SMDS PLCP Layer Transmitter

The SMDS PLCP Layer Transmitter (SPLT ) Block integrates circuitry to support DS1, DS3, E1,

and G.751 E3 based PLCP frame insertion.

The SPLT automatically inserts the framing (A1, A2) and path overhead identification (POHID)

octets and provides registers or automatic generation of the F1, B1, G1, M2, M1, and C1 octets.

Registers are provided for the path user channel octet (F1) and the path status octet (G1). The bit

interleaved parity octet (B1) and the FEBE subfield are automatically inserted.

The DQDB management information octets, M1 and M2 are generated. The type 0 and type 1

patterns described in TA-TSY-000772 are automatically inserted. The type 1 page counter may be

reset using a register bit in the SPLT Configuration Register. Note: This feature is not required for

the ATM Forum compliant DS3 UNI. For this application, the M1 and M2 octets must be set to

all zeros.

The PLCP transmit frame C1 cycle/stuff counter octet and the transmit stuffing pattern can be

referenced to the REF8KI input pin. Alternately, a fixed stuffing pattern may be inserted into the

C1 cycle/stuff counter octet. A looped timing operating mode is provided where the transmit

PLCP timing is derived from the received timing. In this mode, the C1 stuffing is generated based

on the received stuffing pattern as determined by the SPLR block. When DS1 or E1 PLCP format

is enabled, the pattern 00H is inserted.

When DS3 PLCP format is enabled, the C1 octet indicates the phase of the 375 µs nibble stuffing

opportunity cycle. During frame one of the three frame cycle, the pattern FFH is inserted in the

C1 octet, indicating a 13 nibble trailer length. During frame two, the pattern 00H is inserted,

indicating a 14 nibble trailer length. During frame three, the pattern 66H or 99H is inserted,

indicating a 13 or 14 nibble trailer length respectively.

When configured for G.751 E3 PLCP frame format, the C1 octet is used to indicate the number of

octets stuffed in the trailer. The Table 5 shows the C1 octet pattern for each of the possible octet

stuff lengths:

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