PM7347 datasheet(63/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt

status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status

FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained

a non-integer number of bytes.

10.6

PMON Performance Monitor Accumulator

The PMON Block interfaces directly with either the DS3 Framer (T3-FRMR) to accumulate LCV

events, parity error (PERR) events, path parity error (CPERR) events, FEBE events, excess zeros

(EXZS), and framing bit error (FERR) events using the saturating counters:

• The E3 Framer (E3-FRMR) to accumulate LCV, PERR (in G.832 mode), FEBE and FERR

events, or

• The J2 Framer (J2-FRMR) to accumulate LCVs, CRC errors (in the PERR counter), Framing

bit errors (FERR), and excess zeros (EXZS).

The PMON stops accumulating error signals from the E3, DS3, or J2 Framers once frame

synchronization is lost.

When an accumulation interval is signaled by a write to the PMON Register address space or a

write to the S/UNI-JET Identification, Master Reset, and Global Monitor Update Register, the

PMON transfers the current counter values into microprocessor-accessible holding registers and

resets the counters to begin collecting error events for the next interval. The counters are reset in

such a manner that error events occurring during the reset period are not missed.

When counter data is transferred into the holding registers, an interrupt will be generated if it has

been enabled. If the holding registers have not been read since the last interrupt, an overrun status

bit is set. Also provided is a register to indicate changes in the PMON counters since the last

accumulation interval.

10.7

SPLR PLCP Layer Receiver

The PLCP Layer Receiver (SPLR) Block integrates circuitry to support DS1, DS3, E1, and G.751

E3 PLCP frame processing. The SPLR provides framing for PLCP based transmission formats.

The SPLR frames to DS1, DS3, E1, and G.751 E3 based PLCP frames with maximum average

reframe times of 635 µs, 22 µs, 483 µs, and 32 µs respectively. Framing is declared (OOF is

removed) upon finding two valid, consecutive sets of framing (A1 and A2) octets and two valid

and sequential path overhead identifier (POHID) octets. While framed, the A1, A2, and POHID

octets are examined. OOF is declared when an error is detected in both the A1 and A2 octets or

when two consecutive POHID octets are found in error. LOF is declared when an OOF state

persists for more than 25 ms, 1 ms, 20 ms, or 1 ms for DS1, DS3, E1, or G.751 E3 PLCP formats

respectively. If the OOF events are intermittent, the LOF counter is decremented at a rate 1/12

(DS3 PLCP), 1/10 (E1, DS1 PLCP) or 1/9(G.751 E3 PLCP) of the incrementing rate. LOF is thus

removed when an in-frame state persists for more than 250 ms for a DS1 signal, 12 ms for a DS3

signal, 200 ms for an E1 signal, or 9 ms for a G.751 E3 signal. When LOF is declared, PLCP

reframe is initiated.

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