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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

J2 extended LOF detection is provided as recommended by ITU-T G.783 with programmable

integration periods of 1 ms, 2 ms, or 3 ms. While integrating up to assert LOF, the counter will

integrate up when the framer asserts an OOF condition and integrates down when the framer de-

asserts the OOF condition. Once an LOF is asserted, the framer must not assert OOF for the

entire integration period before LOF is de-asserted.

10.4

RBOC Bit-Oriented Code Detector

Note: The Bit-Oriented Code Detector is only used in DS3 C-bit Parity or J2 mode.

The Bit-Oriented Code Detector (RBOC) Block detects the presence of 63 of the 64 possible bit-

oriented codes (BOCs) contained in the DS3 C-bit parity far-end alarm and control (FEAC)

channel or in the J2 datalink signal stream. The 64th code ("111111") is similar to the HDLC flag

sequence and is ignored.

BOCs are received on the FEAC channel as 16-bit sequences each consisting of eight ones, a

zero, six code bits, and a trailing zero ("111111110xxxxxx0"). BOCs are validated when repeated

at least 10 times. The RBOC can be enabled to declare a code valid if it has been observed for

eight out of 10 times or for four out of five times, as specified by the AVC bit in the RBOC

Configuration/Interrupt Enable Register. The RBOC declares that the code is removed if two code

sequences containing code values that are different from the detected code are received in a

moving window of 10 code periods.

Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC bits are set to

all-ones ("111111") when no valid code is detected. The RBOC can be programmed to generate

an interrupt when a detected code has been validated and when the code is removed.

10.5

RDLC PMDL Receiver

The RDLC is a microprocessor peripheral used to receive LAPD/HDLC frames on any serial

HDLC bit stream that provides data and clock information such as the DS3 C-bit parity Path

Maintenance Data Link, the E3 G.832 Network Requirement byte or the General Purpose data

link (selectable using the RNETOP bit in the S/UNI-JET Data Link and FERF/RAI Control

The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros

on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check

sequence (FCS).

In the address matching mode, only those packets whose first data byte matches one of two

programmable bytes or the universal address (all ones) are stored in the FIFO. The two least

significant bits of the address comparison can be masked for LAPD SAPI matching.

Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a

programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are

detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.

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