Data Sheet

ADTR1107

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. C | 7 of 27

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 4, 6, 11, 13 to

16, 18, 22

GND

Ground. Solder these pins to a low impedance ground plane.

2

RX_OUT

Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω.

5

TX_IN

Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω.

7

VGG_PA

Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier.

8

VDD_PA

Power Amplifier Drain Bias Voltage.

9, 10

NIC

No Internal Connection. Solder these pins to a low impedance ground plane.

12

CPLR_OUT

Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power.

17

ANT

RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω.

19

VDD_SW

SPDT Switch Positive Bias Voltage.

20

CTRL_SW

Switch Digital Control. This pin controls the state of the SPDT switch.

21

VSS_SW

SPDT Switch Negative Bias Voltage.

23

VGG_LNA

LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is supplied with 0 V or is

connected to ground, the LNA runs in self bias mode at a typical current of 80 mA.

24

VDD_LNA

LNA Drain Voltage Bias.

EPAD

Exposed Pad. Must be connected to RF/dc ground.

INTERFACE SCHEMATICS

Figure 3. GND Interface Schematic

Figure 4. ANT Interface Schematic

Figure 5. CTRL_SW and VDD_SW Interface Schematic

Figure 6. VDD_PA Interface Schematic

Figure 7. VGG_PA Interface Schematic

Figure 8. VDD_LNA Interface Schematic