PIC16F946-ESLASHMLQTP datasheet(40/330 Pages) MICROCHIP

40 / 330 page

PIC16F913/914/916/917/946

DS41250F-page 38

2.2.2.7

PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0

U-0

R/W-0

U-0

R/W-0

OSFIF

C2IF

C1IF

LCDIF

—LVDIF

—CCP2IF(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

= System clock operating

bit 6

C2IF: Comparator C2 Interrupt Flag bit

= Comparator output (C2OUT bit) has changed (must be cleared in software)

= Comparator output (C2OUT bit) has not changed

bit 5

C1IF: Comparator C1 Interrupt Flag bit

= Comparator output (C1OUT bit) has changed (must be cleared in software)

= Comparator output (C1OUT bit) has not changed

bit 4

LCDIF: LCD Module Interrupt bit

= LCD has generated an interrupt

= LCD has not generated an interrupt

bit 3

Unimplemented: Read as ‘0’

bit 2

LVDIF: Low Voltage Detect Interrupt Flag bit

= LVD has generated an interrupt

= LVD has not generated an interrupt

bit 1

Unimplemented: Read as ‘0’

bit 0

CCP2IF: CCP2 Interrupt Flag bit(1)

Capture Mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare Mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

Note 1:

PIC16F914/PIC16F917/PIC16F946 only.

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