PIC16F631 datasheet(191/294 Pages) MICROCHIP

191 / 294 page

DS41262D-page 189

PIC16F631/677/685/687/689/690

13.12.4

TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and pin RB6/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR

by setting bit CKP (SSPCON<4>). The master must

monitor the SCL pin prior to asserting another clock

pulse. The slave devices may be holding off the master

by stretching the clock. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 13-10).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the data transfer is complete. When the ACK is latched

by the slave, the slave logic is reset (resets SSPSTAT

occurrence of the Start bit. If the SDA line was low

(ACK), the transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR

setting bit CKP.

FIGURE 13-10:

I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

ACK

Transmitting Data

R/W = 1

Receiving Address

56789

123

Cleared in software

SSPBUF is written in software

From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

Data in

sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

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