PIC16F631 datasheet(154/294 Pages) MICROCHIP

154 / 294 page

PIC16F631/677/685/687/689/690

DS41262D-page 152

12.1.1.4

TSR Status

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

12.1.1.5

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREG. All nine bits

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 12.1.2.7 “Address

Detection” for more information on the Address mode.

12.1.1.6

Asynchronous Transmission Set-up:

Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 12.3 “EUSART Baud

Rate Generator (BRG)”).

Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

If interrupts are desired, set the TXIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE and PEIE bits of the

INTCON register are also set.

If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 12-3:

ASYNCHRONOUS TRANSMISSION

FIGURE 12-4:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1

Stop bit

Word 1

Transmit Shift Reg

Start bit

bit 0

bit 1

bit 7/8

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC4/C2OUT/TX/CK

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

RC4/C2OUT/TX/CK

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Word 2

Word 1

Word 2

Start bit

Stop bit

Start bit

Transmit Shift Reg.

Word 1

Word 2

bit 0

bit 1

bit 7/8

bit 0

Note:

This timing diagram shows two consecutive transmissions.

1 TCY

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