PIC16F631 datasheet(104/294 Pages) MICROCHIP

104 / 294 page

PIC16F631/677/685/687/689/690

DS41262D-page 102

8.9

Comparator SR Latch

The SR Latch module provides additional control of the

comparator outputs. The module consists of a single

SR latch and output multiplexers. The SR latch can be

set, reset or toggled by the comparator outputs. The SR

latch may also be set or reset, independent of

comparator output, by control bits in the SRCON control

whether the latch outputs or the comparator outputs are

directed to the I/O port logic for eventual output to a pin.

8.9.1

LATCH OPERATION

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. Each latch input is connected to a

comparator output and a software controlled pulse

generator. The latch can be set by C1OUT or the PULSS

bit of the SRCON register. The latch can be reset by

C2OUT or the PULSR bit of the SRCON register. The

latch is reset-dominant, therefore, if both Set and Reset

inputs are high, the latch will go to the Reset state. Both

the PULSS and PULSR bits are self resetting which

means that a single write to either of the bits is all that is

necessary to complete a latch set or reset operation.

8.9.2

LATCH OUTPUT

The SR<1:0> bits of the SRCON register control the

latch output multiplexers and determine four possible

output configurations. In these four configurations, the

CxOUT I/O port logic is connected to:

• C1OUT and C2OUT

• C1OUT and SR latch Q

• C2OUT and SR latch Q

• SR latch Q and Q

After any Reset, the default output configuration is the

unlatched C1OUT and C2OUT mode. This maintains

compatibility with devices that do not have the SR latch

feature.

The applicable TRIS bits of the corresponding ports

must be cleared to enable the port pin output drivers.

Additionally, the CxOE comparator output enable bits of

the CMxCON0 registers must be set in order to make the

comparator or latch outputs available on the output pins.

The latch configuration enable states are completely

independent of the enable states for the comparators.

FIGURE 8-7:

SR LATCH SIMPLIFIED BLOCK DIAGRAM

C1SEN

SR0

PULSS

C2REN

PULSR

SR1

Note

If R = 1 and S = 1 simultaneously, Q = 0, Q = 1

Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.

Output shown for reference only. See I/O port pin block diagram for more detail.

Pulse

Gen(2)

Pulse

Gen(2)

SYNCC2OUT (from comparator)

C1OUT (from comparator)

C2OE

C2OUT pin(3)

C1OE

C1OUT pin(3)

MUX

Latch(1)

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