TDA9143 datasheet(24/40 Pages) PHILIPS

24 / 40 page

1996 Jan 17

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

TDA9143

bandwidth at

−1 dB

any input to any output;

CL =15pF

−−

MHz

tclamp

internal Y clamping time constant

−

FAST SWITCH F(PIN 18)

VIL

LOW level input voltage

UV switched on

−

0.5

VIH

HIGH level input voltage

RGB switched on

0.9

−

3.0

switching delay

between F and YUV

−−

EXTERNAL CLAMP INPUT (PIN 17)

VIL

LOW level input voltage (pin CLP)

no clamping

−

0.6

VIH

HIGH level input voltage (pin CLP)

clamping

2.4

−

5.5

tW(clamp)

clamping pulse width

note 6

1.8

3.5

−µs

Vos(clamp)

clamping offset voltage on UV outputs

−−

input impedance

ECL = 1

−−

Ω

Colour matrix

voltage gain

from R to Yout

0.41

0.43

0.45

from G to Yout

0.80

0.84

0.88

from B to Yout

0.15

0.16

0.17

from R to Uout

0.41

0.43

0.45

from G to Uout

0.80

0.84

0.88

from B to Uout

1.21

1.27

1.33

from R to Vout

0.95

1.00

1.05

from G to Vout

0.80

0.84

0.88

from B to Vout

0.15

0.16

0.17

Output and in/output port

O PORT (PIN 16); OPB/CLP MODE

VOH

HIGH level output voltage

4.0

5.5

VOL

LOW level output voltage

−

0.2

0.4

Isink

sink current

100

−−µA

Isource

source current

100

−−µA

I/O PORT; OPB/CLP MODE

VOH

HIGH level output voltage

−−

VCC

VOL

LOW level output voltage

−

0.2

0.4

Isink

sink current

−−

VIH

HIGH level input voltage

2.0

−−

VIL

LOW level input voltage

−−

0.6

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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