TDA9143 datasheet(22/40 Pages) PHILIPS

22 / 40 page

1996 Jan 17

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

TDA9143

DC output voltage level

−

2.5

−

delay between negative edge of LLC

and positive edge of HA pulse

CL = 15 pF

102040ns

Vertical section

VERTICAL OSCILLATOR

ffr

free running frequency

FORF = 1; divider ratio 628

−

FORF = 0; divider ratio 528

−

fLR

frequency locking range

−

divider locking range

488

625

722

VA OUTPUT (PIN 11); ECL = 0

VOH

HIGH level output voltage

4.0

5.5

VOL

LOW level output voltage

−

0.2

0.4

Isink

sink current

−−

Isource

source current

−−

tW(VA)

VA pulse width

2.5/fH

50 Hz standard

−

160

−µs

3/fH

60 Hz standard

−

192

−µs

delay between start of vertical sync

pulse and positive edge of VA

note 4; see Fig.7

−

−µs

output impedance

ECL = 1

−−

Ω

Sandcastle output (pin 10)

zero level output voltage

0.5

Isink

sink current

0.5

0.7

0.9

HORIZONTAL AND VERTICAL BLANKING

Vbl

blanking voltage level

2.2

2.5

2.8

Isource

source current

0.5

0.7

0.9

Iext

external current required to force the

output to the blanking level

1.0

−

3.0

tW(H)

horizontal blanking pulse width

69 LLC pulses

−

10.0

−µs

delay between start of horizontal

blanking and start of clamping pulse

44 LLC pulses

−

6.4

−µs

CLAMPING PULSE

Vclamp

clamping voltage level

4.2

4.5

4.8

Isource

source current

0.5

0.7

0.9

tW(clamp)

clamping pulse width

25 LLC pulses

−

3.6

−µs

delay between middle sync of input

and start of clamping pulse

note 3

3.0

3.2

3.4

µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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