TDA9143 datasheet(11/40 Pages) PHILIPS

11 / 40 page

1996 Jan 17

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

TDA9143

When the controller is in the NEAR_NORM state it will

move to the COUNT state if it detects the vertical sync

pulse within the NEAR_NORM window (i.e.

622 < LC < 628). If no vertical sync pulse is detected the

controller will move back to the COUNT state when the line

counter reaches LC = 628. The line counter will then be

reset.

When the controller is in the NO_NORM state, it will move

to the COUNT state when it detects a vertical sync pulse

and reset the line counter. If a vertical sync pulse is not

detected before LC = 722 (if the

ϕ1 loop is locked in forced

mode) it will move to the COUNT state and reset the line

counter. If the

ϕ1 loop is not locked the controller will return

to the COUNT state when LC = 628.

The forced mode option keeps the controller in either the

left-hand side (60 Hz) or the right-hand side (50 Hz) of the

state diagram.

Figure 6 illustrates the state diagram of the norm counter

which is an up/down counter that increases its counter

value by 1 if it finds a vertical sync pulse within the selected

window. If not, it decreases the counter value by 1 (or 2,

see Fig.6). In the NEAR_NORM and NORM states the first

correct vertical sync pulse after one or more incorrect

vertical sync pulses is processed as an incorrect pulse.

This procedure prevents the system from staying in the

NEAR_NORM or NORM state if the vertical sync pulse is

correct in the first field and incorrect in the second field.

In case of no sync lock (SLN = 1) the norm counter is reset

to NO_NORM (wide search window), for fast vertical

catching when switching between video sources. Fast

switching between different channels however can still

result in a continuous horizontal sync lock situation, when

the channel is changed before the norm counter has

reached the NORM state. To provide faster vertical

catching in this case, measures have been taken to

prevent the norm counter to count down to zero before

reaching the NO_NORM state (see left-hand of Fig.6). Bus

bit FWW (forced wide window) enables the norm counter

to stay in the NO_NORM state if desired. The

norm/no_norm status is read out by bus bit NRM.

Fig.6 State diagram of the norm counter.

(1) VSP found: count 1 up; no VSP found: count 2 down.

handbook, full pagewidth

MGE041

NORM

NEAR

NORM

NEAR

NORM

NEAR

NORM

< NC ≤ 27

≤ NC < 12

< NC < 26(1)

< NC < 17

< NC < 14

NC = 26

NC = 17

NC = 14

(RESET

NC)

NC = 22

NC = 0

NC = 12

(RESET NC)

norm test area

near_norm test area

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