Data Sheet

AD9914

REGISTER MAP AND BIT DESCRIPTIONS

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Rev. G | 45 of 48

Digital Ramp Lower Limit Register—Address 0x04

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 20. Bit Descriptions for Digital Ramp Lower Limit Register

Bit(s)

Mnemonic

Description

[31:0]

Digital ramp lower limit

32-bit digital ramp lower limit value.

Digital Ramp Upper Limit Register—Address 0x05

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 21. Bit Descriptions for Digital Ramp Limit Register

Bit(s)

Mnemonic

Description

[31:0]

Digital ramp upper limit

32-bit digital ramp upper limit value.

Rising Digital Ramp Step Size Register—Address 0x06

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 22. Bit Descriptions for Rising Digital Ramp Step Size Register

Bit(s)

Mnemonic

Description

[31:0]

Rising digital ramp increment step

size

32-bit digital ramp increment step size value.

Falling Digital Ramp Step Size Register—Address 0x07

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 23. Bit Descriptions for Falling Digital Ramp Step Size Register

Bit(s)

Mnemonic

Description

[31:0]

Falling digital ramp decrement step

size

32-bit digital ramp decrement step size value.

Digital Ramp Rate Register—Address 0x08

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 24. Bit Descriptions for Digital Ramp Rate Register

Bit(s)

Mnemonic

Description

[31:16]

Digital ramp negative slope rate

16-bit digital ramp negative slope value that defines the time interval between decrement values.

[15:0]

Digital ramp positive slope rate

16-bit digital ramp positive slope value that defines the time interval between increment values.

Lower Frequency Jump Register—Address 0x09

This register is effective only if the digital ramp enable bit (0x01[19]) = 1, the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register, and

at least one of the no-dwell bits (CFR2[18:17]) is Logic 0. See the Digital Ramp Generator (DRG) section for details.