Data Sheet

AD9914

REGISTER MAP AND BIT DESCRIPTIONS

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Rev. G | 44 of 48

Control Function Register 3 (CFR3)—Address 0x02

Table 18. Bit Descriptions for CFR3

Bit(s)

Mnemonic

Description

[31:23]

Open

Open.

22

PLL input divider reset

0 = disables the PLL input divider reset function.

1 = resets the PLL input divider.

[21:20]

PLL input divide value

Divides the input REF CLK signal to the PLL by one of three values (2, 4, 8). Bit 17 must be set to Logic 1 to use the

PLL input divider.

00 = disable divider.

01 = divide by 2.

10 = divide by 4.

11 = divide by 8.

19

PLL input doubler select

0 = selects the feedthrough path.

1 = selects the 2× path.

This bit is only meaningful when CFR3[18] = 1 and CFR3[17] = 0.

18

PLL enable

0 = disables the internal PLL.

1 = enables the internal PLL for generating the system clock (the PLL must be calibrated via CFR1[24]).

17

PLL input divider select

0 = Selects the feed through and 2× multiplier paths.

1 = selects the PLL input divider path.

This bit is only meaningful when CFR3[18] = 1.

16

PLL edge select

0 = select rising edge.

1 = select falling edge.

This bit is only meaningful when CFR3[18] = 1, CFR3[17] = 0 and CFR3[19] = 0. The PLL locks to the selected edge of

REF_CLK.

[15:8]

Feedback divider N

The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second part is the fixed divide

by two element in the feedback path. Therefore, the total PLL multiplication value is 2N. The valid N divider range is

10× to 255×. The default N value for Bits[15:8] = 25, which sets the total default PLL multiplication to 50× or 2N.

7

Open

Open.

6

Manual ICP selection

0 = the internal charge pump current is chosen automatically during the VCO calibration routine (default).

1 = the internal charge pump is set manually per Table 7.

[5:3]

ICP

Manual charge pump current selection. See Table 7.

2

Lock detect enable

0 = disables PLL lock detection.

1 = enables PLL lock detection.

[1:0]

Minimum LDW

Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain within before a PLL lock

condition can be read back via Bit 24 in Register 0x00.

00 = 128 REF CLK cycles.

01 = 256 REF CLK cycles.

10 = 512 REF CLK cycles.

11 = 1024 REF CLK cycles.

Control Function Register 4 (CFR4)—Address 0x03

Table 19. Bit Descriptions for DAC

Bit(s)

Mnemonic

Description

[31:27]

Open

Open.

26

Auxiliary divider power‑down

0 = enables the SYNC OUT circuitry.1 = disables the SYNC OUT circuitry.

25

DAC CAL clock power‑down

0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0.1 = disables the DAC CAL clock.

24

DAC CAL enable

1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and any time the internal

system clock is changed.

[23:0]

(See description)

These bits must always be programmed with the default values listed in the default column in Table 15.