AD9914SLASHPCBZ datasheet(33/48 Pages) AD

33 / 48 page

Data Sheet

AD9914

PROGRAMMING AND FUNCTION PINS

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Rev. G | 33 of 48

AD9914 to accommodate applications with wideband modulation

requirements.

Be aware that the frequency, phase, and amplitude changes ap-

plied at the parallel port travel to the DDS core over different

paths, experiencing different propagation times (latency). Therefore,

modulating more than one DDS parameter necessitates setting

the matched latency enable bit in the CFR2 register (0x01[15]) of

the device, which equalizes the latency of each DDS parameter

as it propagates from the parallel port to the DDS core. Note

that high speed modulation requires a DAC reconstruction filter

with sufficient bandwidth to accommodate the instantaneous time

domain transitions.

Because direct access to the DDS parameters occurs via the FTW,

POW, and AMP registers, the IO_UPDATE pin (see Figure 42)

adds another layer of flexibility. That is, by default, 0x00[17] = 0.

Therefore, writing data to the FTW, POW, or AMP registers does

not make the data immediately available to the DDS core. Instead,

the user must assert the IO_UPDATE pin to transfer the data from

the FTW, POW, and AMP registers to the DDS core. Asserting the

IO_UPDATE pin gives the user a level of control over the timing

of when an FTW, POW, or AMP register change is applied to the

DDS core. Note that assertion of IO_UPDATE or changing the state

of the profile select pins (PS2 to PS0) is functionally equivalent.

Furthermore, either action is gated by the rising edge of the internal

SYNC_CLK signal.

However, when the logic levels applied to the function pins (F[3:0])

= 0010 to 1101 (that is, the high speed parallel data port is active),

programming 0x00[17] = 1 activates streaming mode. In streaming

mode, data at the D[31:0] pins is transferred to the FTW, POW,

or AMP register and directly to the DDS core on each rising edge

of the internal SYNC_CLK signal. Thus, streaming mode provides

for wide band modulation by eliminating the need to assert IO_UP-

DATE.

As as example to demonstrate the flexibility of the parallel data port,

suppose an application requires frequency and amplitude modula-

tion with full 32-bit frequency resolution and full 12-bit amplitude

resolution. Note that none of the F[3:0] pin combinations supports

such modulation capability directly. To circumvent this problem, pro-

gram 0x00[17]) = 0 (that is, disable streaming mode). This setting

allows the use of two direct mode cycles of the 32-pin parallel

port, each with a different function pin setting, without affecting the

DDS core until assertion of the IO_UPDATE pin. That is, the first

direct mode cycle constitutes setting the function pins to F[3:0] =

0010, which routes all 32 bits to the FTW register (frequency).

The second direct mode cycle constitutes setting the function pins

to F[3:0] = 0100, which provides full 12-bit access to the AMP

includes the POW register (phase). Therefore, be sure keep the

phase bits unchanged from their previous value. Next, toggle the

IO_UPDATE pin, which synchronously (on the rising edge of the

internal SYNC_CLK signal) transfers the new frequency and phase

values from the FTW and POW registers to the DDS core. This

mode of operation reduces the overall modulation rate by a factor

of three because it requires two direct mode cycles (a minimum

of two SYNC_CLK periods) followed by an IO_UPDATE assertion.

However, this mode still allows modulation sample rates as high as

~49 MSPS.

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