LLCC68 datasheet(23/106 Pages) SEMTECH

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LLCC68

Data Sheet

Rev. 1.0

DS.LLCC68.W.APP

July 2019

23 of 106

Semtech

www.semtech.com

When using the LoRa® modulation with LowDataRateOptimize set to 0x00 (see Table 13-50: "LoRa® ModParam4 -

LowDataRateOptimize" on page 82), the total frequency drift over the packet transmission time should be minimized and

kept lower than Freq_drift_max:

When possible, using LowDataRateOptimize set to 0x01 will significantly relax the total frequency drift over the packet

transmission requirement to 16 x Freq_drift_max.

Note:

Recommendations for heat dissipation techniques to be applied to the PCB designs are given in detail in the application

note AN1200.37 “Recommendations for Best Performance” on www.semtech.com.

In miniaturized design implementations where heat dissipations techniques cannot be implemented or the use of the

LowDataRateOptimize is not supported, the use of a TCXO will provide a more stable clock reference.

4.1.3 XTAL Control Block

The LLCC68 does not require the user to set external foot capacitors on the XTAL supplying the 32 MHz clock. Indeed, the

device is fitted with internal programmable capacitors connected independently to the pins XTA and XTB of the device.

Each capacitor can be set independently, balanced or unbalanced to each other, by 0.47 pF typical steps.

Note when using an XTAL:

At POR or when waking-up from Sleep in cold start mode, the trimming cap registers will be initialized at the value 0x05

(13.6 pF). Once the device is set in STDBY_XOSC mode, the internal state machine will overwrite both registers to the value

0x12 (19.7pF). Therefore, the user must ensure the device is already in STDBY_XOSC mode before changing the trimming

cap values so that they are not overwritten by the state machine.

Note when using a TCXO:

Once the command SetDIO3AsTCXOCtrl(...) is sent to the device, the register controlling the internal cap on XTA will be

automatically changed to 0x2F (33.4 pF) to filter any spurious which could occur and be propagated to the PLL.

Table 4-1: Internal Foot Capacitor Configuration

Typical Values

XTA

0x0911

Each capacitor can be controlled independently

in steps of 0.47 pF added to the minimal value:

0x00 sets the trimming cap to 11.3 pF (minimum)

0x2F sets the trimming cap to 33.4 pF (maximum)

XTB

0x0912

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