M65KA512AB datasheet(13/55 Pages) STMICROELECTRONICS

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M65KA512AB

Operations

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3.3

Burst Write

The Write command is used to switch the device to Burst Write mode (see Section 4.4:

Write command for details). In Burst Write mode the data is input in bursts synchronized

with the clock. Burst Write operations are initiated by driving E, CAS and W Low, VIL, and

RAS High, and VIH, at the positive edge of the clock signal, K.

Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the

A10 Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write

operation is followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), Auto Precharge

is not selected and the row will remain active for subsequent accesses.

BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select

the starting column location.

Refer to Figure 13, Figure 14, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20 for a

detailed description of Burst Write ac waveforms.

3.4

Self Refresh

In Self Refresh mode, the data contained in the Low-Power SDRAM memory array is

retained and refreshed. The Low-Power SDRAM refresh cycles are asynchronous.

All banks must be precharged prior to executing a Self-Refresh operation. The Self-Refresh

mode is entered by driving KE Low (set to ‘0’), with E, RAS, and CAS Low, and W High (set

to ‘1’). When in this mode, the device is not clocked any more.

The Self Refresh mode is exited by driving KE from Low to High, with E High, RAS, CAS

and W Don’t Care, or with E Low and RAS, CAS and W High.

The Self Refresh operation is performed according to the settings of Extended Mode

(Partial Array Self Refresh).

3.5

Auto Refresh

The Auto Refresh mode is used to refresh the Low-Power SDRAM in normal operation

mode whenever needed.

All banks must be precharged prior to executing an Auto Refresh operation.

During the Auto Refresh, the address bits are “Don’t Care”, because the specific address

bits are generated by the internal refresh address counter.

3.6

Power-Down

In Power-Down mode, the current is reduced to the standby current (IDD3P).

All banks must be precharged before entering Power-Down mode. For the memory to enter

the Power-Down mode, KE must be held Low (set to ‘0’), after the Precharge Time tRP, with

E High (set to ‘1’), RAS, CAS and W Don’t Care, or with E Low, RAS, CAS and W High.

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