M65KA512AB datasheet(12/55 Pages) STMICROELECTRONICS

12 / 55 page

Operations

M65KA512AB

12/55

Operations

There are 7 operating modes that control the memory. Each of these is described in this

section, see Table 2: Operating mode, for a summary.

3.1

Power-Up

The Low-Power SDRAM has to be powered up and initialized in a well determined manner.

Power must be applied to VDD and VDDQ simultaneously and, at the same time, the clock

signal must be started. After Power-Up, a minimum initial pause of 200µs is required. From

power-up until the Precharge command is issued, the KE and DQM signals must be held

High. The Precharge command must then be issued to all banks, and 2 or more Auto

Refresh cycles must be executed after the precharge is completed and the minimum tRP is

satisfied. Once these cycles are completed, a Mode Register Set command must be issued

to program the specific operation mode (CAS Latency, Burst Length, etc.). After issuing the

Mode Register Set command, the device will not accept any other command for tRSC. After

issuing the Extended Mode Register Set command the device will not accept any other

command for tRSC.

The device is now ready for normal operation.

Refer to Figure 22 for a detailed description of the Power-Up ac waveforms.

3.2

Burst Read

The Read command is used to switch the device to Burst Read mode (see Section 4.5:

Read command for details). In Burst Read mode the data is output in bursts synchronized

with the clock. Burst Read opertions are initiated by driving E and CAS Low, VIL, W and

RAS High, and VIH, at the positive edge of the clock signal, K.

Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the

A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the

Burst Read operation is followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), the

row will remain active for subsequent accesses.

BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select

the starting column location. The Burst Length, Burst Type, and CAS Latency depend on the

values programmed by issuing a Mode Register Set command (see Section 5.1: Mode

After a Burst Read operation is completed, data outputs become High-Z.

Refer to Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for a

detailed description of Burst Read ac waveforms.

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