AD9163BBCZ datasheet(49/126 Pages) AD

49 / 126 page

Data Sheet

AD9163

Rev. D | Page 49 of 126

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x4B8,

Bits[3:0]. The IRQ event status can be read at Register 0x4BA,

Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA,

Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to

reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to

reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to

reset the ILAS IRQ.

See the Interrupt Request Operation section for more

information.

Configuration Mismatch IRQ

The AD9163 has a configuration mismatch flag that is available as

an IRQ event. Use Register 0x4B9, Bit 0 to enable the mismatch

flag (it is enabled by default), and then use Register 0x4BB, Bit 0

to read back its status and reset the IRQ signal. See the Interrupt

Request Operation section for more information.

The configuration mismatch event flag is high when the link

configuration settings (in Register 0x450 to Register 0x45D) do

not match the JESD204B transmitted settings (Register 0x400 to

This function is different from the good checksum flags in

ted checksum matches a calculated checksum based on the

transmitted settings. The configuration mismatch event ensures

that the transmitted settings match the configured settings.

HARDWARE CONSIDERATIONS

See the Applications Information section for information on

hardware considerations.

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