AD9163BBCZ datasheet(39/126 Pages) AD

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Data Sheet

AD9163

Rev. D | Page 39 of 126

a. Set Register 0x036 = 0. Writing anything to

SYSREF_COUNT resets the count.

b. Set Register 0x034 = 0. Writing anything to

SYNC_LMFC_STAT0 saves the data for readback and

registers the count.

c. Read SYSREF_COUNT from the value from

4. Perform a one-shot sync.

a. Set Register 0x03A = 0x00. Clear one-shot mode if

already enabled.

b. Set Register 0x03A = 0x02. Enable one-shot sync

mode. The state machine enters monitor mode after a

sync occurs.

5. Optionally, read back the sync SYNC_LMFC_STATx

registers to verify that sync completed correctly.

a. Set Register 0x034 = 0. Register 0x034 must be written

to read the value.

b. Read Register 0x035 and Register 0x034 to find the

value of SYNC_LMFC_STATx. It is recommended to

set SYNC_LMFC_STATx to 0 but it can be set to 4, or

a LMFC period in DAC clocks – 4, due to jitter.

6. Optionally, read back the sync SYSREF_PHASEx register

to identify which phase of the divide by 4 was used to

sample SYSREF±. Read Register 0x038 and Register 0x037

as thermometer code. The MSBs of Register 0x037,

Bits[7:4], normally show the thermometer code value.

7. Turn the link on (Register 0x300, Bit 0 = 1).

8. Read back Register 0x302 (dynamic link latency).

9. Repeat the reestablishment of the link several times (Step 1

to Step 7) and note the dynamic link latency values. Based

on the values, program the LMFC delay (Register 0x304) and

the LMFC variable (Register 0x306), and then restart the link.

Table 20. Sync Processing Modes

Sync Processing

Mode

SYNC_MODE (Register 0x03A, Bits[1:0])

No synchronization

0b00

One shot

0b10

Continuous

0b01

Table 21. SYSREF± Jitter Window Tolerance

SYSREF± Jitter Window

Tolerance (DAC Clock Cycles)

SYSREF_JITTER_WINDOW

(Register 0x039, Bits[5:0])1

±½

0x00

±4

0x04

±8

0x08

±12

0x0C

±16

0x10

±20

0x14

+24

0x18

±28

0x1C

The two least significant digits are ignored because the SYSREF± signal is

sampled with a divide by 4 version of the DAC clock. As a result, the jitter

window is set by this divide by 4 clock rather than the DAC clock. It is

recommended that at least a four-DAC clock SYSREF± jitter window be chosen.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout its system. Data traversing from one clock domain

to a different clock domain can lead to ambiguous delays in the

JESD204B link. These ambiguities lead to nonrepeatable latencies

across the link from power cycle to power cycle with each new

link establishment. Section 6 of the JESD204B specification

addresses the issue of deterministic latency with mechanisms

defined as Subclass 1 and Subclass 2.

The AD9163 supports JESD204B Subclass 0 and Subclass 1

operation, but not Subclass 2. Write the subclass to Register 0x458,

Bits[7:5].

Subclass 0

This mode gives deterministic latency to within 32 DAC clock

cycles. It does not require any signal on the SYSREF± pins,

which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same LMFC

cycle and the dual DACs must be synchronized to each other.

Subclass 1

This mode gives deterministic latency and allows the link to be

synced to within four DAC clock periods. It requires an external

SYSREF± signal that is accurately phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.

•

SYSREF± signal distribution skew within the system must

be less than the desired uncertainty.

•

SYSREF± setup and hold time requirements must be met

for each device in the system.

•

The total latency variation across all lanes, links, and

devices must be ≤10 PCLK periods, which includes both

variable delays and the variation in fixed delays from lane

to lane, link to link, and device to device in the system.

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